1. Field of the Invention
This invention relates generally to the manufacture and packaging of semiconductor devices. More particularly, this invention relates to an improved ball grid array (BGA) layout and fabrication method for a semiconductor device package assembly including consolidated common voltage connections to reduce the length of wires for wire bonding, to allow higher number and higher density of pin-count, and to improve the manufacture yield rate thus reduce the manufacturing costs of the semiconductor devices.
2. Description of the Prior Art
As the integrated circuits (ICs) become ever smaller with higher circuit density while handling more complicate functions and processes, the level of technical complexity in packaging and connecting the IC devices on a printed circuit board by the use of electric wires also becomes a more difficult task. Specifically, with the increased number of wires connected to an IC device, the distance between these wires becomes smaller. Potential problem arises when there may be cross-coupling of the variations of the electric-magnetic fields in these wires as the distances between these wires become smaller. Furthermore, with limited surface areas available on an IC dice and on the printed circuit board surrounding the IC dice. It may often require the use of longer electric leads for establishing electric contact with either a ground voltage or other voltage sources and external circuits. The longer length of wires poses potential problems in manufacturing yield and long-term operational reliability.
A package for containing the high speed IC devices is disclosed in an U.S. Pat. No. 5,012,386 by McShane et al. entitled `High Performance Overmolded Electronic Package`. The package has a multiple layers with a built-in cavity. The substrate has a plurality of holes penetrating these multiple layers for the leads to be placed therein for soldering or otherwise electrically connecting to conductive pattern or layers in the substrate. A thermally conductive insert is attached to one side of the substrate. The insert has a pedestal which protrudes through the cavity in the substrate. An electronic component, such as an IC may be mounted on the pedestal and electrically connected to a electrically conductive metal pattern on one of the layers of the substrate. The assembly may then be coated with dielectric material to form a package body. The package also has a thermal insert to aid in dissipating the heat. The package may also have a ground and power planes to provide consistent coplanar leads such that the surface mounting processes may be more uniformly performed.
The package disclosed by McShane et al. provides good protection and enhanced thermal conductivity for the mounting of the electronic device. However, it does not provide a solution to the difficulty that the modern electronic IC devices often require more input, output, input/output (I/O) or other type of pin connections for external interface. The limitation encountered in the prior art can be clearly appreciated by referring to FIG. 1 which is originally included as FIG. 1 in the Patent by McShane et al. Thus the number of leads which need to be connected to the IC device is greatly increased with increased pin counts. Even that the substrate includes a ground or other power planes wherein each plane being set at a specific common voltage, no disclosure is made by McShane et al. to employ the planes of common voltage to solve the difficulty caused by the high density pin counts and the requirement of numerous leads for connection to the IC device.
Lin et al. disclose in another U.S. Pat. No. 5,216,278 entitled `Semiconductor Device Having a Pad Array Carrier Package` (issued on Jun. 1, 1993) a semiconductor device mounted on a carrier substrate. The semiconductor device has a first and a second wiring layers on opposite surface of the carrier substrate interconnected through vias formed in the substrate carrier which provide electric coupling of the semiconductor device to an IC to a mounting substrate through compliant solder balls displaced away from the vias.
The substrate carrier as disclosed by Lin et al. can be made with standard size and provides good heat dissipation. The lead traces formed on independent wiring layers can improve the electrical performance. The electric traces with the specific layout may also be formed prior to the mounting of the electronic component thus reducing the manufacturing cost. However, the semiconductor device as disclosed by Lin et al. (see FIG. 2 from the Patent by Lin et al.) does not provide a electric wire layout to overcome the difficulty for a modern electronic component, e.g., an IC device, when the pin counts for external interfaces are increased thus causing a very high electric wiring density as that shown in FIG. 3. It can be appreciated by a brief comparison of the electric wiring arrangements between FIGS. 2 and 3 that as the pin counts and the density of electric wires increased, it is required to extend the length of the electric wires in order to properly separate the bonding pads on the substrate and the vias on the outer edges of the substrate. The extended length of the electric wires causes an increase in manufacturing cost not only more materials are required for longer wires, also the formation of elongated fine traces with very short distances between these wires reduced the yield rate of good products. The difficulty of making uniform long wires on the substrate also reduces the reliability of the semiconductor device where malfunction of the entire device may be caused by a failure of one of these wires.
Therefore, a need still exists in the art of semiconductor manufacture and packaging to provide a layout configuration and design method to overcome this problem. Specifically, this layout configuration for the electric wire connections must be able to reduce the required length of the leads while providing easy access for external interface, maintaining high level of packaging integrity and improving the manufacturing yield.